In many kinds of integrated circuits, particularly in those related to communications, there is a constant need to use FIFOs. In most cases, a FIFO is utilized to perform a buffering function. For example, in an integrated circuit, a FIFO can be used to buffer data that is being transmitted between two different circuit units controlled by two asynchronous clocking signals.
Similarly, if an integrated circuit is interfaced with an external microcomputer, data can be stored in a FIFO until there is a sufficient accumulation of data to start a continuous transmission of data between the integrated circuit and the microcomputer. Advantageously, this reduces the need for the microcomputer to execute an interrupt process in receiving data from the integrated circuit.
A conventional FIFO 10 is illustrated in FIG. 1. The FIFO 10 of FIG. 1 contains a data storage unit for storing a certain amount of data. Data to be written into the FIFO 10 is represented by DATAIN. Data is written into the FIFO 10 under the control of a clock signal CKIN. Data which is read out of the FIFO is represented by DATAOUT. Data is read out of the FIFO 10 under the control of a clock signal CKOUT. When the FIFO 10 is full and no more data can be written into it, a FULL Signal is generated. Similarly, when all of the data stored in the FIFO 10 is read out, an EMPTY signal is generated.
The internal design of the FIFO 10 of FIG. 1 is schematically illustrated in FIG. 2. As illustrated in FIG. 2, the FIFO 10 comprises a memory section 12 and a centralized control unit 14. The memory section 12 comprises a plurality of regularly arranged memory units 16. The control unit 14 controls the writing of data into and the reading of data out of the memory units 16 in response to the clock signals CKIN and CKOUT. The control unit 14 also generates the FULL and EMPTY signals when the memory units 16 are all FULL or all EMPTY.
When a FIFO is incorporated into an integrated circuit, the design of a central control unit is often a major undertaking. In particular, a separate design of the central control unit must usually be made for each FIFO of different size (i.e. different data storage capacity). In addition, because the centralized control unit is not modular, extra layout effort is required for an integrated circuit implementation.
One possible approach to this problem is modularization (see, e.g., Ward et al, U.S. Pat. No. 4,839,866 and Huang et al, U.S. Pat. No. 4,592,019). In particular, it would be highly advantageous if FIFO modules comprising a modular memory section and a modular control section could be devised so that a FIFO of arbitrary size could be produced simply by connecting the appropriate number of modules. It is an object of the present invention to provide such FIFO modules. It is a further object of the invention to provide such FIFO modules with a simple and efficient distributed control section that is especially easy to implement in an integrated circuit.